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dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 for more products and information please visit our web site at www.austinsemiconductor.com available as military specifications ? smd 5962-90847 ? mil-std-883 1 meg x 4 dram fast page mode dram features ? industry standard x4 pinout, timing, functions, and packages ? high-performance, cmos silicon-gate process ? single +5v10% power supply ? low-power, 2.5mw standby; 300mw active, typical ? all inputs, outputs, and clocks are fully ttl and cmos compatible ? 1,024-cycle refresh distributed across 16ms ? refresh modes: ras\-only, cas\-before-ras\ (cbr), and hidden ? fast page mode access cycle ? cbr with we\ a high (jedec test mode capable via wcbr) options marking ? timing 70ns access -7 80ns access -8 100ns access -10 120ns access -12 ? packages ceramic dip (300 mil) cn no. 103 ceramic dip (400 mil) c no. 104 ceramic lcc* ecn no. 202 ceramic zip cz no. 400 ceramic soj ecj no. 504 ceramic gull wing ecg no. 600 *note: if solder-dip and lead-attach is desired on lcc packages, lead-attach must be done prior to the solder- dip operation. pin assignment (top view) 20-pin dip (c, cn) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dq1 dq2 we\ ras\ a9 a0 a1 a2 a3 vcc vss dq4 dq3 cas\ oe\ a8 a7 a6 a5 a4 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 dq1 dq2 we\ ras\ a9 a0 a1 a2 a3 vcc vss dq4 dq3 cas\ oe\ a8 a7 a6 a5 a4 20-pin soj (ecj), 20-pin lcc (ecn), & 20-pin gull wing (ecg) general description the mt4c4001j is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. during read or write cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (a0-a9) at a time. ras\ is used to latch the first 10 bits and cas\ the later 10 bits. a read or write cycle is selected with the we\ input. a logic high on we\ dictates read mode while a logic low on we\ dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we\ or cas\, whichever occurs last. if we\ goes low prior to cas\ going low, the output pin(s) remain open (high-z) until the next cas\ cycle. if we\ goes low after data reaches the output pin(s), qs are activated and retain the selected cell data as long as cas\ remains low (regardless of we\ or ras\). this late we\ pulse results in a read-write cycle. the four data inputs and four data outputs are routed through four pins using common i/o and pin direction is controlled by we\ and oe\. fast-page- mode operations allow faster data operations (read, write, or read-modify-write) within a row address (a0-a9) defined page boundary. the fast page mode (continued) 20-pin dip (cz) oe\ 1 dq3 3 vss 5 dq2 7 ras\ 9 a0 11 a2 13 vcc 15 a5 17 a7 19 2 cas\ 4 dq4 6 dq1 8 we\ 10 a9 12 a1 14 a3 16 a4 18 a6 20 a8
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 general description (cont.) cycle is always initiated with a row address strobe-in by ras\ followed by a column address strobed-in by cas\. cas\ may be toggled-in by holding ras\ low and strobing-in different column addresses, thus executing faster memory cycles. returning ras\ high terminates the fast page mode operation. returning ras\ and cas\ high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the ras\ high time. memory cell data is retained in its corrected stated by maintaining power and executing any ras\ cycle (read, write, ras\-only, cas\-before-ras\, or hidden refresh) so that all 1,024 combinations of ras\ addresses (a0-a9) are executed at least every 16ms, regardless of sequence. the cbr refresh cycle will invoke the internal refresh counter for automatic ras\ addressing. functional block diagram fast page mode we\ dq1 cas\ dq2 dq3 dq4 oe\ vcc a0 vss a1 a2 a3 a4 a5 a6 a7 a8 a9 ras\ no. 2 clock generator no. 1 clock generator column address buffer refresh controller refresh counter row address buffers (10) *early-write detection circuit data in buffer data out buffer column decoder sense amplifiers i/o gating memory array row decoder 1024 1024 x 4 1024 4 4 4 4 10 10 10 10 10 note: we\ low prior to cas\ low, ew detection circuit output is a high (early-write) cas\ low prior to we\ low, ew detection circuit output is a low (late-write)
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 truth table data in/out t r t c dq1-dq4 hh xxxxx high-z l l h l row col data out l l l x row col data in llh ll h row col data out/data in 1st cycle l h l h l row col data out 2nd cycle l h l h l n/a col data out 1st cycle l h l l x row col data in 2nd cycle l h l l x n/a col data in 1st cycle l h lh ll h row col data out/data in 2nd cycle l h lh ll h n/a col data out/data in l h x x row n/a high-z read l h l l h l row col data out write l h l l l x row col data in h l l h x x x high-z hidden refresh cas\-before-ras\ refresh fast-page-mode read-write fast-page-mode read fast-page-mode early-write ras\-only refresh standby read early-write read-write addresses function ras\ cas\ we\ oe\
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 absolute maximum ratings* voltage on any pin relative to vss.................-1.0v to +7.0v storage temperature.......................................-65 o c to +150 o c power dissipation.................................................................1w short circuit output current...........................................50ma lead temperature (soldering 5 seconds).....................+270 o c *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (notes: 1, 3, 4, 6, 7) (-55c < t a < 125c; v c c = 5v 10%) parameter/condition sym min max units notes supply voltage v cc 4.5 5.5 v input high (logic 1) voltage, all inputs v ih 2.4 v cc +0.5 v input low (logic 0) voltage, all inputs v il -0.5 0.8 v input leakage current any input 0v < v in < 5.5v vcc = 5.5v (all other pints not under test = 0v) i i -5 5 a output leakage current (q is disabled, 0v < v out < 5.5v) vcc = 5.5v i oz -5 5 a v oh 2.4 v v ol 0.4 v output levels output high voltage (i out = -5ma) output low voltage (i out = 4.2ma) parameter/condition sym -7 -8 -10 -12 units notes standby current (ttl) (ras\ = cas\ = v ih ) i cc1 4444ma standby current (cmos) (ras\ = cas\ = v cc -0.2v; all other inputs = v cc -0.2v) i cc2 2222ma operating current: random read/write average power-supply current (ras\, cas\, address cycling: t rc = t rc (min)) i cc3 85 75 65 70 ma 3, 4 operating current: fast page mode average power-supply current (ras\ = v il , cas\, address cycling: t pc = t pc (min)) i cc4 60 50 45 40 ma 3, 4 refresh current: ras\-only average power-supply current (ras\ cycling, cas\ = v ih : t rc = t rc (min)) i cc5 85 75 65 70 ma 3 refresh current: cas\-before-ras\ average power-supply current (ras\, cas\, address cycling: t rc = t rc (min)) i cc6 85 75 65 70 ma 3, 5 max
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 capacitance electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55c < t c < 125c; v c c = 5v 10%) parameter sym min max units notes input capacitance: a0-a10 c i1 7pf2 input capacitance: ras\, cas\, we\, oe\ c i2 7pf2 input/output capacitance: dq c io 8pf2 parameter sym min max min max min max min max units notes random read or write cycle time t rc 130 150 190 220 ns read-write cycle time t rwc 180 200 240 255 ns fast-page-mode read or write cycle time t pc 40 45 55 70 ns fast-page-mode read-write cycle time t prwc 90 90 110 140 ns access time from ras\ t rac 70 80 90 120 ns 14 access time from cas\ t cac 20 20 25 30 ns 15 access time from column address t aa 35 40 45 60 ns access time from cas\ precharge t cpa 35 40 45 60 ns ras\ pulse width t ras 70 10,000 80 10,000 100 10,000 120 100,000 ns ras\ pulse width (fast page mode) t rasp 70 100,000 80 100,000 100 100,000 120 100,000 ns ras\ hold time t rsh 20 20 25 30 ns ras\ precharge time t rp 50 60 70 90 ns cas\ pulse width t cas 20 10,000 20 10,000 25 10,000 30 ns cas\ hold time t csh 70 80 100 120 ns cas\ precharge time t cpn 10 10 12 15 ns 16 cas\ precharge time (fast page mode) t cp 10 10 12 15 ns ras\ to cas\ delay time t rcd 20 50 20 60 25 75 25 90 ns 17 cas\ to ras\ precharge time t crp 5 5 5 10 ns row address setup time t asr 0000ns row address hold time t rah 10 10 15 15 ns ras\ to column address delay time t rad 15 35 15 40 20 50 20 60 ns 18 column address setup time t asc 0000ns column address hold time t cah 15 15 20 25 ns column address hold time (referenced to ras\) t ar 50 60 70 85 ns column address to ras\ lead time t ral 35 40 50 60 ns read command setup time t rcs 0000ns read command hold time (referenced to cas\) t rch 0000ns19 read command hold time (referenced to ras\) t rrh 0000ns19 cas\ to output in low-z t clz 0000ns output buffer turn-off delay t off 0 20 0 20 0 20 0 20 ns 20 we\ command setup time t wcs 0000ns 21, 27 -7 -8 -10 -12
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 electrical characteristics and recommended ac operating conditions (notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55c < t c < 125c; v c c = 5v 10%) parameter sym min max min max min max min max units notes write command hold time t wch 15 15 20 25 ns write command hold time (referenced to ras\) t wcr 50 60 70 80 ns write command pulse width t wp 15 15 20 25 ns write command to ras\ lead time t rwl 20 20 25 30 ns write commend to cas\ lead time t cwl 20 20 25 30 ns data-in setup time t ds 0000ns22 data-in hold time t dh 12 15 18 25 ns 22 data-in hold time (referenced to ras\) t dhr 50 60 70 90 ns ras\ to we\ delay time t rwd 95 105 130 140 ns 21 column address to we\ delay time t awd 60 65 80 90 ns 21 cas\ to we\ delay time t cwd 45 45 55 60 ns 21 transition time (rise or fall) t t 3 50 3 50 3 50 3 50 ns refresh period (1,024 cycles) t ref 16 16 16 16 ns ras\ to cas\ precharge time t rpc 0000ns cas\ setup time (cas\-before-ras\ refresh) t csr 5 101010ns5 cas\ hold time (cas\-before-ras\ refresh) t chr 10 15 20 25 ns 5 we\ hold time (cas\-before-ras\ refresh) t wrh 10 10 10 10 ns 25, 28 we\ setup time (cas\-before-ras\ refresh) t wrp 10 10 10 10 ns 25, 28 we\ hold time (wcbr test cycle) t wth 10 10 10 10 ns 25, 28 we\ setup time (wcbr test cycle) t wts 10 10 10 10 ns 25, 28 oe\ setup prior to ras during hidden refresh cycle t ord 0000ns output disable t od 15 20 25 25 ns 27 output enable t oe 15 20 25 25 ns 23 oe\ hold time from we\ during read-modify-write cycle t oeh 20 20 25 25 ns 26 -7 -8 -10 -12
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 notes: 1. all voltages referenced to vss. 2. this parameter is sampled, not 100% tested. capacitance is measured with vcc=5v, f=1 mhz at less than 50mvrms, t a = 25c 3c, vbias = 2.4v applied to each input and output individually with remaining inputs and outputs open. 3. icc is dependent on cycle rates. 4. icc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the output open. 5. enables on-chip refresh and address counters. 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55c < t a < 125c) is assured. 7. an initial pause of 100s is required after power-up followed by eight ras\ refresh cycles (ras\-only or cbr with we\ high) before proper device operation is assured. the eight ras\ cycle wake-up should be repeated any time the 16ms refresh requirement is exceeded. 8. ac characteristics assume t t = 5ns. 9. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 10. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 11. if cas\ = v ih , data outputs (dqs) are high-z. 12. if cas\ = v il , data outputs (dqs) may contain data from the last valid read cycle. 13. measured with a load equivalent to two ttl gates and 100pf. 14. assumes that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 15. assumes that t rcd > t rcd (max) 16. if cas\ is low at the falling edge of ras\, dqs will be maintained from the previous cycle. to initiate a new cycle and clear the data out buffer, cas\ must be pulsed high for t cpn . 17. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 18. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 19. either t rch or t rrh must be satisfied for a read cycle. 20. t off (max) defines the time at which the output achieves the open circuit conditions and is not referenced to v oh or v ol . 21. t wcs , t rwd , t awd , and t cwd are not restrictive operating parameters. t wcs applies to early-write cycles. t rwd , t awd , and t cwd apply to read-modify-write cycles. if t wcs > t wcs (min), the cycle is an early-write cycles and the data output will remain an open circuit throughout the entire cycle. if t rwd > t rwd (min), t awd > t awd (min) and t cwd > t cwd (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. oe\ held high and we\ taken low after cas\ goes low results in a late-write (oe\ controlled) cycle. t wcs , t rwd , t cwd , and t awd are not applicable in a late-write cycle. 22. these parameters are referenced to cas\ leading edge in early-write cycle and we\ leading edge in late-write cycles and we\ leading edge in late-write or read-modify-write cycle. 23. if oe\ is tied permanently low, late-write or read-modify-write operations are not possible. 24. a hidden refresh may also be performed after a write cycle. in this case, we\=low and oe\=high. 25. t wts and t wth are setup and hold specifications for the we\ pin being held low to enable the jedec test mode (with cbr timing constraints). these two parameters are the inverts of t wrp and t wrh in the cbr refresh cycle. 26. late-write and read-modify-write cycles must have both t od and t oeh met (oe\ high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas\ remains low and oe\ is taken back low after t oeh is met. if cas\ goes high prior to oe\ going back low, the dqs will remain open. 27. the dqs open during read cycles once t od or t off occur. if cas\ goes high first, oe\ becomes a dont care. if oe\ goes high and cas\ stays low, oe\ is not a dont care; and the dqs will provide the previously read data if oe\ is taken back low (while cas\ remains low). 28. jedec test mode only.
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 read cycle early-write cycle
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 fast-page-mode read cycle read-write cycle (late-write and read-modify-write cycles)
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 fast-page-mode early-write cycle fast-page-mode read-write cycle (late-write and read-modify-write cycles) *t pc = late-write cycle t prwc = fast read-modify-write cycle
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 ras\-only refresh cycle (addr = a0-a9; we\ = dont care) cas\-before-ras\ refresh cycle (a0-a9, and oe\ = dont care) hidden refresh cycle 24 (we\ = high, oe\ = low)
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 4 meg power-up and refresh constraints the eia/jedec 4 meg dram introduces two potential incompatibilities compared to the previous generation 1 meg dram. the incompatibilities involve refresh and power-up. understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 meg and 4 meg. refresh the most commonly used refresh mode of the 1 meg is the cbr (cas\-before-ras\) refresh cycle. the cbr for the 1 meg specifies the we\ pin as a dont care. the 4 meg, on the other hand, specifies the cbr refresh mode with the we\ pin held at a voltage high level. a cbr cycle with we\ low will put the 4 meg into the jedec specified test mode (wcbr). power-up the 4 meg jedec test mode constraint may introduce another problem. the 1 meg power-up cycle requires a 100s delay followed by any eight ras\ cycles. the 4 meg power-up is more restrictive in that eight ras\-only or cbr refresh (we\ held high) cycles must be used. the restriction is needed since the 4 meg may power-up in the jedec specified test mode and must exit out of the test mode. the only way to exit the 4 meg jedec test mode is with either a ras\-only or a cbr refresh cycle (we\ held high). summary 1. the 1 meg cbr refresh allows the we\ pin to be dont care while the 4 meg cbr requires we\ to be high. 2. the eight ras\ wake-up cycles on the 1 meg may be any valid ras\ cycle while the 4 meg may only use ras\-only or cbr refresh cycles (we\ held high). comparison of 4 meg test mode and wcbr to 1 meg cbr
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 mechanical definitions* asi case #103 (package designator cn) smd 5962-90847, case outline r note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. d e pin 1 a q l e b b2 s1 ea c r min max a --- 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d --- 1.060 e 0.220 0.310 ea e q 0.015 0.070 l 0.125 0.200 s1 0.005 --- r 90 105 symbol smd specifications 0.100 bsc 0.300 bsc
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 mechanical definitions* asi case #104 (package designator c) smd 5962-90847, case outline u note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. ea c a q l e b b2 s1 d e d1 pin 1 min max a --- 0.175 b 0.015 0.021 b2 0.045 0.065 c 0.008 0.014 d 0.980 1.030 d1 0.890 0.910 e 0.380 0.410 ea 0.385 0.420 e q 0.015 0.060 l 0.125 0.200 s1 --- 0.070 symbol smd specifications 0.100 bsc
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 mechanical definitions* asi case #400 (package designator cz) smd 5962-90847, case outline n note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. min max a 0.355 0.405 b 0.016 0.023 b2 0.035 0.045 c 0.008 0.015 e 0.045 0.055 ea 0.085 0.115 d 1.035 1.065 e 0.100 0.130 l 0.125 0.200 l1 0.015 0.050 symbol smd specifications
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 * all measurements are in inches. asi case #202 (package designator ecn) smd 5962-90847, case outline t note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. e d a a1 e1 l e b l1 s r min max a 0.060 0.080 a1 b 0.022 0.028 d 0.343 0.357 e 0.665 0.685 e1 0.590 0.610 e l 0.045 0.055 l1 0.080 0.100 r 0.006 0.010 s 0.025 0.050 0.050 typ symbol smd specifications 0.035 typ
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 17 asi case #504 (package designator ecj) mechanical definition* *all measurements are in inches. a a1 e b d e d1 b2 b1 min max a 0.120 0.140 a1 0.066 0.078 b 0.022 0.028 b1 b2 0.090 0.11 d 0.665 0.685 d1 0.592 0.608 e 0.345 0.355 e1 0.345 0.360 e 0.045 0.055 l 0.057 0.063 symbol asi specifications 0.050 typ l e1
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 18 asi case #600 (package designator ecg) mechanical definition* *all measurements are in inches. min max a 0.120 0.140 a1 0.066 0.078 b 0.022 0.028 b1 b2 0.090 0.110 d 0.665 0.685 d1 0.592 0.608 e 0.345 0.355 e1 0.482 0.498 e2 0.442 0.458 e 0.045 0.055 e1 l 0.057 0.063 symbol asi package specifications 0.050 typ 0.014 dia. typ
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 19 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c example: mt4c4001jcn-8/883c example: mt4c4001jc-12/883c device number package t yp e speed ns process device number package t yp e speed ns process mt4c4001j cn -7 /* mt4c4001j c -7 /* mt4c4001j cn -8 /* mt4c4001j c -8 /* mt4c4001j cn -10 /* mt4c4001j c -10 /* mt4c4001j cn -12 /* mt4c4001j c -12 /* example: mt4c4001jcz-7/883c example: mt4c4001jecn-10/xt device number package t yp e speed ns process device number package t yp e speed ns process mt4c4001j cz -7 /* mt4c4001j ecn -7 /* mt4c4001j cz -8 /* mt4c4001j ecn -8 /* mt4c4001j cz -10 /* mt4c4001j ecn -10 /* mt4c4001j cz -12 /* mt4c4001j ecn -12 /* example: mt4c4001jecj-7/it example: mt4c4001jecg-12/it device number package t yp e speed ns process device number package t yp e speed ns process mt4c4001j ecj -7 /* mt4c4001j ecg -7 /* mt4c4001j ecj -8 /* mt4c4001j ecg -8 /* mt4c4001j ecj -10 /* mt4c4001j ecg -10 /* mt4c4001j ecj -12 /* mt4c4001j ecg -12 /*
dram mt4c4001j austin semiconductor, inc. mt4c4001j rev. 1.0 9/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 20 * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd. asi to dscc part number cross reference* asi package designator cz asi part # smd part # mt4c4001jcz-8/883c 5962-9084703mna mt4c4001jcz-10/883c 5962-9084702mna mt4c4001jcz-12/883c 5962-9084701mna asi package designator c asi part # smd part # mt4c4001jc-8/883c 5962-9084703mua mt4c4001jc-10/883c 5962-9084702mua mt4c4001jc-12/883c 5962-9084701mua asi package designator cn asi part # smd part # mt4c4001jcn-8/883c 5962-9084703mra mt4c4001jcn-10/883c 5962-9084702mra mt4c4001jcn-12/883c 5962-9084701mra asi package designator ecn asi part # smd part # mt4c4001jecn-8/883c 5962-9084703mta mt4c4001jecn-10/883c 5962-9084702mta mt4c4001jecn-12/883c 5962-9084701mta

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